It’s All About Timing: From Precision RTL Synthesis to Quartus II Software

For today’s advanced FPGAs, accurate timing constraints are important to obtain optimal synthesis and place-and-route results, and play a critical role during timing analysis and verification. The Precision RTL Synthesis timing-driven synthesis engine supports detailed timing constraints such as clock characteristics and timing exceptions. The TimeQuest timing analyzer in the Altera Quartus II software is a powerful ASICstyle static timing analysis tool that validates FPGA timing performance using Synopsys Design Constraints (SDC) format.